Design And Reuse

EXTOLL announces Availability of Industry´s first 16G UCIe PHY IP in GlobalFoundries 22FDX/22FDX+ Ready for Customer Integration

EXTOLL, a leading provider of high-speed and ultra-low-power SerDes and Chiplet connectivity, announces the availability and readiness for customer integration of the industry´s first 16G UCIe PHY IP ...
Design And Reuse

Aeva Adopts Cadence Tensilica Vision DSP to Advance Lidar Performance and Efficiency

Cadence (Nasdaq: CDNS) today announced that Aeva, a leader in next-generation sensing and perception systems, has licensed Cadence ® Tensilica ® Vision DSP IP to accelerate signal processing in its 4D ...
Design And Reuse

Chips&Media Completes Development of Next-Gen 'AV2' HW Decoder IP

HW RTL release in May with active commercial licensing talks underway with major North American clients ...
Design-Reuse

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You must be registered with the D&R website to view the full search results, including: Complete datasheets for IP Core products Contact information for IP Core ...