Electronic Design

Functional Verification Tool Gains Link To SystemVerilog Assertions

With the addition of a standard assertion-language link, the 360 Module Verifier (360 MV), a functional verification environment, is equipped to fully leverage both SystemVerilog assertions and Open ...
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Business Wire

Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa

Using Questa's native implementation of SystemVerilog, we were able to deploy a very sophisticated coverage-driven, constrained-random verification environment that fully utilized the advanced ...
Semiconductor Engineering

Easier Assertion Development And Debug With Simulation Replay

Assertions and assertion IP (AIP) are a core part of the register transfer level (RTL) verification environment for all modern chip development projects. Assertions can be considered as statements of ...